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| 9312 Introducing Maverick EP9312 Jeff Klaas - Director of Engineering Presented at the Embedded Processor Forum San Jose, California, June 13, 2000 9312 Digital Audio Jukebox 2 9312 The Challenge Create a cost-effective solution for a digital audio jukebox meeting the following goals: Quick time-to-market 10x Real-time MP3 encoding Hardware based content security High-quality audio Home network enabled Robust I/O for OEM flexibility Low cost storage options Flexible user interface 3 9312 The Solution Create a cost-effective solution for a digital audio jukebox meeting the following goals: Quick time-to-market 10x Real-time MP3 encoding Hardware based content security Low cost storage options Home network enabled High-quality audio Robust I/O for OEM flexibility Flexible user interface ARM 920T Core MaverickCrunchTM Engine MaverickLockTM Security EIDE Controller Ethernet MAC I2S 24-bit audio Interface USB, UARTs, IrDA LCD Controller Touchscreen Controller Keypad Interface The right feature set and performance level at the right price-point! 4 9312 ARM920T Processor 200 MHz Processor Clock 16KB instruction & data caches 64 entry instruction & data TLB Independent lockable pages Windows CE compatible MMU Processor Core Serial Ports 3 Port USB Host UARTs (3) w/ HDLC I2 S SPI Ethernet MAC Bus Bridge CrunchTM Engine Interrupts and GPIO Clocks and Timers ARM920T Flexible interrupts & GPIO Up to 64 interrupts 32 priority levels 16 expanded GPIO signals 16KB I 16KB D Cache Cache User Interface MMU DMA W/ CRC Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F Clocks & Timers Dual PLL produces all clocks 6 timers & clocks + RTC 5 EIDE I/F Unified SDRAM I/F Memory & Storage 9312 MaverickCrunch 3 Port USB Host Ethernet MAC TM Engine I2 S SPI Serial Ports General Architecture for Market Specific Extensions Balanced approach to algorithm efficiency Floating point, integer and signal processing instruction set Hardware Interlocks to remove implementation details Full tools support from Cygnus UARTs (3) w/ HDLC Bus Bridge CrunchTM Engine Interrupts and GPIO Clocks and Timers ARM920T 16KB I 16KB D Cache Cache User Interface MMU DMA W/ CRC Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F It ain't PICCOLO! EIDE I/F Unified SDRAM I/F Memory & Storage 6 9312 MaverickCrunch TM Engine (Cont) ARM920T Co-Processor Interface Hardware Support IEEE Single/Double Floating Point 32/64 Bit Integer Add/Multiply/Compare Integer MAC 32-bit input with 72 bit accumulate Integer Shifts Float Integer Conversion Maverick Crunch 16 x 64b Register File with Interlocks Source Bus Implementation Register file is 0 stall at CPU speed < 2mm2 in 0.25u Hardware forwarding and interlock Float/Int Compare Float Multiply / Integer MAC 4 x 72b accumulators Float Adder Destination Bus 7 9312 MaverickCrunch TM Engine (Cont) Single Code Stack for Control and Computation ARM handles loop and addressing Maverick Crunch handles compute Integer MAC (32bit X 32bit + 72bit --> 72bit) for high MIP filters IEEE-754 floating point provides dynamic range 16x64b register file plus 4x72b accumulators ;Floating point example ;R2 points to start of filter data block ;R3 points to start of filter coefficient block ;R4 points to scale factors ;R5 points to stored value ;Loop setup ;N/4 Loop Software unrolled for minimum stalls loop: SUBS R0, R0, #1 ;decrement loop count CMP R0, #0 ;Test loop counter CFLDR32 MVFX0, [R2] ,#4 ;Load Coprocessor regs w/data CFLDR32 MVFX1, [R3] ,#4 ;Load Coprocessor regs w/data CFLDR32 MVFX2, [R2] ,#4 ;Load Coprocessor regs w/data CFLDR32 MVFX3, [R3] ,#4 ;Load Coprocessor regs w/data CFLDR32 MVFX4, [R2] ,#4 ;Load Coprocessor regs w/data CFMADDA32 MVAX0, MVAX0, MVFX0, MVFX1 ;FX0*FX1+AX0->AX0 CFLDR32 MVFX0, [R3] ,#4 ;Load Coprocessor regs w/data CFMADDA32 MVAX0, MVAX0, MVFX2, MVFX3 ;FX2*FX3+AX0->AX0 CFLDR32 MVFX1, [R2] ,#4 ;Load Coprocessor regs w/data CFLDR32 MVFX2, [R3] ,#4 ;Load Coprocessor regs w/data CFMADDA32 MVAX0, MVAX0, MVFX4, MVFX0 ;FX4*FX0+AX0->AX0 CFMADDA32 MVAX0, MVAX0, MVFX1, MVFX2 ;FX1*FX2+AX0->AX0 BNE loop ;Exit if equal ;Finish calculations NOP NOP CFMV64A MVDX10, MVAX0 CFLDRS MVF13, [R4] CFCVT64S MVF11, MVDX10 CFMULS MVF14, MVF11, MVF13 CFSTRS MVF14, [R5] High Precision FIR Followed by Scale 17 * (N/4) + 26 with Maverick Crunch >6X improvement over ARM9 CPU 8 ;Any Non-coprocessor Inst ;Any Non-coprocessor Inst ;Convert i72A->i64, sat & rnd ;Load coprocessor scale factor ;Convert i64->f32 ;Multiply two f32's ;final result stored to mem 9312 Secrets stay Secret MaverickLockTM Security Serial Ports 3 Port USB Host UARTs (3) w/ HDLC I2 S SPI Ethernet MAC Unique emulation technology allows CPU to create locked Cache/MMU entries without internal or external memory 256 bits of laser fuses provide on chip permanent IDs and passwords Security boot firmware and private passwords are "invisible" except when IC is "Locked" Debug and manufacturing test modes disabled when IC is "Locked" Encrypted Firmware Bus Bridge CrunchTM Engine Interrupts and GPIO Clocks and Timers ARM920T 16KB I 16KB D Cache Cache User Interface MMU DMA W/ CRC Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F EIDE I/F Unified SDRAM I/F Memory & Storage 9 9312 MaverickLockTM Security (Cont) ARM 920T Instruction Cache Locked Date Cache Locked ARM 9tdmi CPU Single IC provides secure hardware environment General architecture that can be used by partner security vendors Combination of boot ROM, laser fuses and gate level IP Multiple security vendors can co-exist in same system Instruction Table Locked Data Table Locked Boot ROM SDMI ID Security 1 Password Security 2 Password Manufacturing Code Laser Fuse Arrays Security Code Hardware Security Code 2 Security Code 1 10 9312 Single Crystal / Multiple Clocks External Clock Wide choice of input sources 3.6864 MHz 4.0 MHz 12.288 MHz Many other viable options OSC 3.6864 MHz 4.0000 MHz 12.288 MHz Clock Divider Clock Divider Clock Divider Multiple clock requirements Independent processor & video clocks 48 MHz - USB and IrDA 18.432 MHz - IrDA 25 MHz - Ethernet 3.6864 MHz- UARTs 48 KHz Audio (3.072 MHz * 2, 3, or 4) PLL PLL ARM USB 48 MHz IrDA-F 48 MHz Video 1-133 MHz Ethernet 25 MHz Divider Divider Divider Divider Divider Divider Divider Divider UART 7.3728 MHz SPI 3.6864 MHz Audio 3.072 MHz Irda-M 18.432 MHz Implementation Dual cascadable PLLs Glitch-free enable/disable Programmable frequency control Programmable phase control 11 9312 Memory & Storage Interfaces Serial Ports 3 Port USB Host Ethernet MAC UARTs (3) w/ HDLC I2 S SPI SDRAM interface (unified memory) 1-4 banks of 66 or 100 MHz SDRAM 16 or 32-bit data path Separate display refresh port Bus Bridge CrunchTM Engine Interrupts and GPIO Clocks and Timers EIDE interface Up to UDMA-33 performance Supports two devices (CD & hard drive) ARM920T 16KB I 16KB D Cache Cache User Interface MMU DMA W/ CRC Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F General purpose memory interface ROM SRAM Flash Memory 8 chip selects 12 EIDE I/F Unified SDRAM I/F Memory & Storage 9312 Serial Communications Ports Serial Ports 3 Port USB Host Ethernet MAC UARTs (3) w/ HDLC I2 S SPI Ethernet Media Access Controller Media independent interface to external PHY 1, 10, 100 Mbps operation HPNA 1.0 compatible Interrupts and GPIO Clocks and Timers Bus Bridge CrunchTM Engine 3 port USB host Integrated USB PHYs USB 1.0 protocol ARM920T 16KB I 16KB D Cache Cache User Interface Audio & telephony Interfaces directly to I2S codec Interfaces directly to serial soft modem Alternate configuration as SPI DMA W/ CRC MMU Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F Three 16550 compatible UARTs UART with HDLC UART with modem & HDLC UART with slow, medium, and fast IrDA 13 EIDE I/F Unified SDRAM I/F Memory & Storage 9312 LCD interface 4, 8, 16, 18 bits per pixel Dedicated SDRAM memory port Pulse width modulated brightness control 6-bit DAC for LCD contrast control User Interfaces Serial Ports 3 Port USB Host UARTs (3) w/ HDLC I2 S SPI Ethernet MAC Bus Bridge CrunchTM Engine Interrupts and GPIO Clocks and Timers Touchscreen interface 4, 5, or 8-wire resistive screen Touchscreen interrupt provided Onboard ADC input ARM920T 16KB I 16KB D Cache Cache User Interface MMU DMA W/ CRC Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F 8 x 8 keyboard scan Interrupt generated on each new key stroke Keyscan register cleared each time it is read Hardware debouncing EIDE I/F Unified SDRAM I/F Memory & Storage 14 9312 q q q q q q q q Vital Statistics Transistor count ~ 5.7 million Process - 0.25u, single poly, 4 metal (6SF) Supply voltages - 2.5V core, 3.3V pads Processor speed - 200 MHz Bus speed - 100 MHz Package - 20x20 PBGA, 352 pin Pads - 332 on 65u pitch Power dissipation - <1.5W 15 9312 Digital Audio Jukebox Serial Ports I2S Codec SPI DAA 3 Port USB Host Ethernet MAC UARTs (3) w/ HDLC I2 S SPI HPNA IR Keyboard or Remote Control Bus Bridge CrunchTM Engine Front Panel Keypad LCD Panel DMA W/ CRC Interrupts and GPIO Clocks and Timers ARM920T 16KB I 16KB D Cache Cache Maverick EP9312 User Interface MMU Maverick LockTM Boot ROM SRAM & Flash I/F Touch Screen & Keypad Interface LCD I/F SDRAM EEPROM FLASH EIDE I/F Unified SDRAM I/F Memory & Storage 16 |
Price & Availability of EP9312
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